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| ? semiconductor components industries, llc, 2010 october, 2010 ? rev. 1 1 publication order number: ncp372/d ncp372 positive and negative overvoltage protection controller with internal low r on nmos fets and status flag the ncp372 is able to disconnect systems from its output pin when wrong operating conditions are detected at it?s input. the system is both positive and negative overvoltage protected up to 28 v. this device uses internal nmos, and therefore, no external device is necessary, reducing the system cost and the pcb area of the application board. the ncp372 is able to instantaneously disconnect the output from the input, due to integrated low r on power nmos, if the input voltage exceeds the overvoltage threshold (ovlo) or undervoltage threshold (uvlo). at powerup ( en pin = low level), the v out turns on 30 ms after the v in exceeds the undervoltage threshold. the ncp372 provides a negative going flag ( flag ) output, which alerts the system that a fault has occurred. in addition, the device has esd ? protected input (15 kv air) when bypassed with a 1.0 f or larger capacitor. features ? overvoltage protection up to 28 v ? negative voltage protection down to ? 28 v ? reverse current blocking ? on ? chip low r ds(on) nmos transistor: typical 130 m ? overvoltage lockout (ovlo) ? undervoltage lockout (uvlo) ? soft ? start ? alert flag output ? shutdown en input ? compliance to iec61000 ? 4 ? 2 (level 4) 8.0 kv (contact) 15 kv (air) ? esd ratings: machine model = b human body model = 2 ? 12 lead llga 3x3 mm package ? this is a pb ? free and halogen ? free device applications ? cell phones ? camera phones ? digital still cameras ? personal digital assistant ? mp3 players ? gps marking diagram a = assembly location l = wafer lot y = year w = work week = pb ? free package http://onsemi.com 12 pin llga mu suffix case 513ak out out flag en nc gnd in in gnd res res res ncp372 (top view) 12 11 10 9 8 7 1 2 3 4 5 6 ncai 372 alyw (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information 1 pin connections
ncp372 http://onsemi.com 2 typical application circuit and functional block diagram 10k 1 f 4.7 f li+battery gnd wall adapter ncp372 1 2 3 8 9 10 7 11 12 figure 1. t ypical application circuit in in gnd gnd out out 0 flag charger system en en flag en flag res res res 4 5 6 u1 nc figure 2. functional block diagram gate driver charge pump control logic and timer uvlo ovlo thermal shutdown en block vref input en gnd flag output ncp372 http://onsemi.com 3 pin function description pin name type description 1, 2 in power input voltage pins. these pins are connected to the power supply. a 1 f low esr ceramic capacitor, or larger, must be connected between these pins and gnd. the two in pins must be hardwired to common supply. 3 gnd power main ground 4 res input reserved pin. this pin must be connected to gnd. 5 res input reserved pin. this pin must be connected to gnd. 6 res input reserved pin. this pin must be connected to gnd. 7 gnd power this pin must be directly hardwired to gnd or through a pull down resistor with a 1 m maximum value. 8 nc nc not connected 9 en input enable pin. the device enters into shutdown mode when this pin is tied to a high level. in this case the output is disconnected from the input. to allow normal functionality, the en pin shall be connected to gnd to a pull ? down or to an i/o pin. this pin does not have an impact on the fault detection. 10 flag output fault indication pin. this pin allows an external system to detect fault condition. the pin goes low when input voltage exceeds ovlo threshold, drops below uvlo threshold, or internal temperature exceeds thermal shutdown limit. since the pin is open drain functionality, an external pull up resistor to vbat must be added (10 k minimum value). 11,12 out output output voltage pin. this pin follows in pins when ?no input fault? is detected. the output is disconnected from the v in power supply when the input voltage is under the uvlo threshold or above ovlo threshold or thermal shutdown limit is exceeded. 13 pad1 power the pad1 is used to dissipate the internal mosfet thermal energy and must be soldered to an isolated pcb area. the area must not be connected to any potential other than a completely isolated one. see pcb recommendations on page 10. maximum ratings rating symbol value unit minimum v oltage (in to gnd) vmin in ? 30 v minimum v oltage (all others to gnd) vmin ? 0.3 v maximum voltage (in to gnd) vmax in 30 v maximum voltage (out to gnd) vmax out 10 v maximum voltage (all others to gnd) vmax 7 v maximum dc current imax 2.5 a thermal resistance, junction ? to ? air, (note 1) r ja 200 c/w operating ambient temperature range t a ? 40 to +85 c storage temperature range t stg ? 65 to +150 c junction operating temperature t j 150 c esd withstand v oltage (iec 61000 ? 4 ? 2) human body model (hbm), model = 2, (note 2) machine model (mm) model = b, (note 3) vesd 15kv air, 8kv contact 2000v 200v kv v v moisture sensitivity msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the r ja is highly dependent on the pcb heat sink area (connected to pad1). see pcb recommendation paragraph. 2. human body model, 100 pf discharged through a 1.5 k resistor following specification jesd22/a114. 3. machine model, 200 pf discharged through all pins following specification jesd22/a115. ncp372 http://onsemi.com 4 electrical characteristics (v in = 5 v, minimum/maximum limits at ? 40 c < t a < +85 c unless otherwise noted. t ypical values are at t a = +25 c) characteristics symbols conditions min typ max unit input voltage range v in en = low or high, v out = 0 v ? 28 28 v input v oltage vin min en = low or high, v out = 4.25v ? 24 v undervoltage lockout threshold uvlo vin falls below uvlo threshold 2.6 2.7 2.8 v undervoltage lockout hysteresis uvlo hyst v in rises above uvlo threshold + uvlo hyst 45 60 75 mv over voltage lockout threshold NCP372MUAITXG ovlo v in rises above ovlo threshold 6.0 6.3 6.6 v overvoltage lockout hysteresis ovlo hyst v in falls below to ovlo ? ovlo hyst 60 80 100 mv v in to v out resistance r ds(on) v in = 5 v, en = low, load connected to v out v in = 5 v, en = low, load connected to v out @ 25 c 130 130 220 200 m input standby current idd std no load. en = high, v in connected 90 170 a input supply quiescent current idd in 25 c overtemperature range 200 260 310 a flag output low voltage vol flag 1.2 v < v in < uvlo sink 50 a on flag pin 30 400 mv v in > ovlo, sink 1 ma on flag pin 400 flag leakage current flag leak flag level = 5.5 v 1.0 na en voltage high v ihen 1.2 v en voltage low v ilen 0.55 v en leakage current en leak v in connected v in disconnected 200 1.0 na thermal shutdown t emperature t sd 150 c thermal shutdown hysteresis t sdhyst 30 c timings start up delay t on from v in > uvlo to v out 0.3 v 20 30 40 ms flag going up delay t start from v out > 0.3 v to flag = 1.2 v 20 30 40 ms turn off delay t off from v in > ovlo to v out 0.3 v v in increasing from 5 v to 8 v at 3 v/ s 1.5 5.0 s alert delay t stop from v in > ovlo to flag 0.4 v see figure 3 and 9 v in increasing from 5 v to 8 v at 3 v/ s 1.5 s disable time t dis en = 0.4 v to 1.2 v to v out 0.3 v 2.5 s note: electrical parameters are guaranteed by correlation across the full range of temperature. ncp372 http://onsemi.com 5 timing diagrams flag v out v in uvlo t on 0.3 v t start 1.2 v ncp372 http://onsemi.com 7 typical operating characteristics figure 13. r ds(on) vs. temperature figure 14. r ds(on) vs. v in figure 15. quiescent current vs. v in from ? 30 v to +30 v, enable mode figure 16. quiescent current vs. v in from ? 30 v to +30 v, disable mode temperature ( c) v in (v) 7.5 6.5 5.5 4.5 3.5 0 40 60 100 120 140 160 100 0 ? 50 100 150 200 r ds(on) (m ) r ds(on) (m ) 50 150 80 250 300 2.5 0 50 en = low 20 180 200 en = low iq vs vin @ vout open (/en=low) ? 400 ? 200 0 200 400 600 800 ? 30 ? 20 ? 10 0 10 20 30 vin (v) iq ( a ) temp= ? 40 c temp= ? 25 c temp= 0 c temp= 25 c temp= 85 c temp = 125 c iq vs vin @ vout open (/en= high) ? 400 ? 200 0 200 400 600 800 ? 30 ? 20 ? 10 0 10 20 30 vin (v) iq ( a ) temp= ? 40 c temp= ? 25 c temp= 0 c temp= 25 c temp= 85 c temp = 125 c ncp372 http://onsemi.com 8 operation the ncp372 provides overvoltage protection for positive and negative voltages, up to 28 v or down to ? 28 v. the negative protection is ensured by an internal low r ds(on) nmos fet. a second internal low r ds(on) nmos fet protects the systems (i.e.: charger) connected on the v out pin, against positive overvoltage. at powerup, with en pin = low, the output rises t on seconds after the input overtakes the undervoltage uvlo (figure 3). the ncp372 provides a flag output, which alerts the system that a fault has occurred. the flag signal rises t start seconds after the output signal rises. flag pin is an open drain output. undervoltage lockout (uvlo) to ensure proper operation under any condition, the device has a built ? in undervoltage lockout (uvlo) circuit. during v in positive going slope, the output remains disconnected from input until v in voltage is 2.7 v nominal. the flag output remains low as long as v in does not reach uvlo threshold. this circuit has a built in hysteresis to provide noise immunity to transient conditions . overvoltage lockout (ovlo) to protect connected systems on v out pin from overvoltage, the device has a built ? in overvoltage lockout (ovlo) circuit. during overvoltage condition, the output remains disabled until the input voltage exceeds 6.3 v. flag output remains low until v in is higher than ovlo. this circuit has a built in hysteresis to provide noise immunity to transient conditions . flag output the ncp372 provides a flag output, which alerts external systems that a fault has occurred. this pin goes low as soon the ovlo threshold is exceeded or when the v in level is below the uvlo threshold. when v in level recovers normal condition, flag goes high, after t start delay following the output response. the pin is an open drain output, thus a pullup resistor (typically 1.0 m , minimum 10 k ) must be provided to v cc . the flag level always reflects v in status, even if the device is turned off (en = 1). en input to enable normal operation, the en pin shall be forced low or connected to ground. a high level on the pin, disconnects out pin from in pin. en does not overdrive an ovlo or uvlo fault. negative voltage and reverse current the built ? in nmos protects the downstream system from negative voltages occurring on in pin down to ? 28 v. the same nmos avoids reverse currents that could discharge the battery. when a fault occurs, the output is disconnected from in pin and flag goes low. ncp372 http://onsemi.com 9 timer check check v in flag = low timer count timer check v in < uvlo or v in > ovlo check en check en v out = v in flag = high check v in v out = open flag = high check v in figure 17. state machine ovlo > v in > uvlo t < t on t = t on reset timer v out = 0 flag = low reset timer v in < uvlo or v in > ovlo v out = 0 flag = low timer count uvlo < v in < ovlo en = 0 en = 1 v in < uvlo or v in > ovlo uvlo < v in < ovlo en = 0 en = 1 t = t start v out = open v in < uvlo or v in > ovlo t < t start uvlo < v in < ovlo v out = v in ncp372 http://onsemi.com 10 thermal shutdown protection in case of internal overheating, the integrated thermal shutdown protection turns off the internal mosfets in order to instantaneously decrease the device temperature. the thermal threshold has been set at 150 c flag then goes low to inform the mcu. as the thermal hysteresis is 30 c, the mosfets will turn on as soon the device temperature falls below 120 c. if the fault event is still present, the temperature increase engages the thermal shutdown again until the fault event disappears. pcb recommendations since the ncp372 integrates 2.5 a n ? mosfets, pcb rules must be respected to properly evacuate the heat out of the silicon. from an applications standpoint, pad1 of the ncp372 package should be connected to an isolated pcb area to increase the heat transfer if necessary. in any case, pad1 should be not connected to any other potential or gnd other than the isolated extra copper surface. to assist in the design of the transfer plane connected to pad1, figure 18 shows the copper area required with respect to r ja . figure 18. copper heat spread area 0 50 100 150 200 250 0 100 200 300 400 500 600 700 0.5 1 1.5 2 2.5 0 power curve with pcb cu thk 1 oz power curve with pcb cu thk 2 oz ja curve with pcb cu thk 2 oz ja curve with pcb cu thk 1 oz copper heat spread area (mm 2 ) maximum ta ( c/w) esd tests the ncp372 conforms to the iec61000 ? 4 ? 2, level 4 on the input pin. a 1 f (i.e murata grm188r61e105ka12d) must be placed close to th e in pins. if the iec61000 ? 4 ? 2 is not a requirement, a 100 nf/25 v must be placed between in and gnd. the above configuration supports 15 kv (air) and 8 kv (contact) at the input per iec61000 ? 4 ? 2 (level 4). please refer to figure 19 for the iec61000 ? 4 ? 2 electrostatic discharge waveform. figure 19. i peak = f(t)/iec61000 ? 4 ? 2 ncp372 http://onsemi.com 11 r ds(on) and dropout the ncp372 includes two internal low r ds(on) n ? mosfets to protect the system, connected on out pin, from overvoltage, negative voltage and reverse current protection. during normal operation, the r ds(on) characteristics of the n ? mosfets give rise to low losses on v out pin. as example: r load = 8 , vin= 5 v. r ds(on) = 155 m . i out = 800 ma. v out = 4.905 v nmos losses = r ds(on) x i out 2 = 0.155 x 0.8 2 = 0.0992 w ordering information device marking package shipping ? NCP372MUAITXG ncai 372 llga12 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd801 1/d. selection guide the ncp372 can be available in several undervoltage and overvoltage options. part number is designated as follows: a ncp372muxxtxg bc d code contents a uvlo typical threshold a: a = 2.7 v b ovlo typical threshold b: i = 6.3 v c tape & reel type c: x = 3000 d d: g = pb ? free ncp372 http://onsemi.com 12 package dimensions llga12 3x3, 0.5p case 513ak ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? a d e b c 0.15 pin one 2x reference 2x top view side view bottom view a l d2 e2 c c 0.15 c 0.10 c 0.08 12x a1 seating plane e 12x note 3 b 12x 0.10 c 0.05 c a b b dim min max millimeters a 0.50 0.60 a1 0.00 0.05 b 0.20 0.30 d 3.00 bsc d2 2.60 2.80 e 3.00 bsc e2 1.90 2.10 e 0.50 bsc k 0.20 ??? l 0.25 0.35 1 6 12 7 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* 12x 0.43 3.30 0.50 pitch 2.05 0.50 2.75 1 k 12x dimensions: millimeters 0.30 11x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp372/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative the products described herein (ncp372), may be covered by one or more u.s. patents. there may be other patents pending. |
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